Design-Reuse

Improving ASIC Design Verification using FPGAs and Structured ASICs

Structured ASICs require developers to re-program only the top level metal layers when customizing their designs, enabling faster development time and low unit cost. However, many structured ASICs ...
Semiconductor Engineering

Beyond The Water Cooler: 2020 Report On IC/ASIC Design And Verification Trends

Verification and design engineers like to talk shop and discuss their experiences and visions. But even though engineers sharing stories around the water cooler (whatever form that takes—conferences, ...
Design-Reuse

ProDesign's CHIPit Verification System Selected by Micronas for Complex Consumer SoC Designs

Increasing System Sales Validates ProDesign's High-Speed Prototyping Concept SAN JOSE, Calif. & MUNICH, Germany--Dec. 19, 2005--ProDesign, a leading supplier of high-speed ASIC and SoC verification ...
Outlookindia

Bridging The Talent Gap In ASIC Design, Verification, And Silicon Validation

As technology continues to evolve, the need for semiconductor chips also increases. The semiconductor industry lies underneath much of the technological progress, powering devices and systems that ...
Semiconductor Engineering

Verification In Crisis

Why is it still so hard to ensure good quality sign-off happens without leaving behind bugs in silicon? The answer, according to my colleagues at DVCon, is highly nuanced. The industry has been ...
EDN

Pre-configured DFT structures can simplify ASIC design, verification

Steven Kawamoto, Sr. Marketing Manager, Custom LSI Solutions Unit, Gaku Ogura, Sr. Marketing Manager, Design Solutions Center, Richard Lee, Design Engineer, Design ...