Layering protocols are modeled using layering structures that mirror the protocol layers. There are significant challenges in modelling verification components for layering protocols such as (1) reuse ...
More processors on SoCs means more sophisticated cache control. This article describes formal techniques for verifying cache coherency for the ARM AMBA AXI Coherency Extensions (ACE) protocol. Fig 1.
As leading system-on-chip (SoC) designs incorporate multiple complex protocols, verification IP (VIP) has become a critical component of the verification environment, enabling engineers to reach their ...
Sun's engineers modeled a complex cache-coherence protocol, with parallelism and multi-threading, for a high-performance processor. They also used a commercial formal property-checking tool from ...
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