EDN

FPGA-Based FIR Filters using Distributed Arithmetic

M. Martinez-Peir, R. Colom, F. Ballester, and R. Gadea are teachers with a focus on digital applications at the Technical University of Valencia, Spain. They are currently working on video compression ...
Electronics Weekly

DSP versus FPGA

In considering the design option for DSP vs. FPGA it is helpful to compare both architectures in a FIR filter application, writes Reg Zatrepalek One of the most widely used digital signal-processing ...
EDN

PCI digitizer boards get FPGA-based FIR filters

Montreal, Canada—Digitizer maker Gage Applied Technologies is debuting FIR (finite impulse response) filters in FPGAs (field programmable gate arrays) in its line of 14-bit digitizers. The FIR filters ...
Hackaday

FIR filter

Digital filters are always an interesting topic, and they are especially attractive with FPGAs. [Pabolo] has been working with them in a series of blog posts. The latest covers an 8th order FIR filter ...
Design-Reuse

Systolic FIR Filter Based FPGA

In this paper, we first review in detail the basic building blocks of reconfigurable devices, essentially, the field-programmable gate arrays, then we describes a high-speed, reconfigurable Systolic ...
Design-Reuse

Optimizing Up/Down Conversion with FPGA Techniques

Digital upconverters (DUCs) and digital downconverters (DDCs) are important components of every modern wireless base station design. While many DUC and DDC designs are available, there is a clear call ...