Semiconductor Engineering

Formal Verification Of Synthesizable C++/SystemC Designs

High-level synthesis (HLS) is a design flow in which design intent is described at a higher level of abstraction than RTL, such as in SystemC/C++ or MATLAB. HLS tools are expected to synthesize this ...
Semiconductor Engineering

High-Level Synthesis Enables The Next Generation Of Edge AI Accelerators

AI is becoming pervasive. But the ever increasing complexity is a challenge for IoT systems. Achieving the highest levels of performance and efficiency in edge AI means going beyond software and off ...
Nature

High-Level Synthesis and Design Space Exploration

High-Level Synthesis (HLS) has emerged as a pivotal technology in the transformation of algorithmic descriptions into efficient hardware designs. Coupled with Design Space Exploration (DSE), HLS ...
Electronic Design

In Adding Control-Logic Support, A High-Level Synthesis Tool Goes Full Chip

High-level synthesis (HLS), or the notion of synthesizing a design into RTL from a higher level of abstraction, has been gaining currency among design teams. For some time now, there have been ...
Electronic Design

Synopsys Jumps Into ESL-Synthesis Pool

Synopsys's Synphony high-level synthesis (HLS) tool takes in algorithmic expressions of functionality written in The MathWorks' Matlab (M) language and outputs RTL that is optimized for timing, area, ...
EDN

Synthesis needs to change to serve modern chip design

As EDA tools evolve, the resulting products try to increase automation. Unfortunately, the last great advance was from schematics to language-based design starting with the first synthesis tools in ...