insideHPC

Universal Coding of the Reals: Alternatives to IEEE Floating Point

In this video from the Conference on Next Generation Arithmetic (CoNGA) conference in Singapore, Peter Lindstrom from Lawrence Livermore National Laboratory presents: Universal Coding of the Reals: ...
EDN

Tutorial: Floating-point arithmetic on FPGAs

[Editor's note: For an intro to fixed-point math, see Fixed-Point DSP and Algorithm Implementation. For a comparison of fixed- and floating-point hardware, see Fixed vs. floating point: a surprisingly ...
Design-Reuse

Single- and double-precision IEEE-754 floating-point unit

The GRFPU is an IEEE-754 compliant floating-point unit, supporting both single and double precision operands. The pipelined design combines high throu ...
Design-Reuse

How to Reduce FPGA Logic Cell Usage by >x5 for Floating-Point FFTs

Here we provide rational for using Centar’s floating-point IP core for the new Altera Arria 10 and Stratix 10 FPGA platforms. After a short contextual discussion section, a comparison of various FFT ...