Semiconductor Engineering

Extending The Benefits Of UVM To Include AMS: An Update On Accellera’s UVM-AMS Standard Development

SoC teams can be divided up into design and verification groups. For digital designs, the Universal Verification Methodology (UVM), initially developed by Accellera and now standardized as IEEE 1800.2 ...
EDN

Breker Verification Systems Unleashes the SystemUVM Initiative to Empower UVM Engineering

Breker Verification Systems used the opening of DVCon U.S. today to unveil SystemUVM, a framework designed to simplify specification model composition for test content synthesis with a ...
Semiconductor Engineering

Universal Verification Methodology Running Out Of Steam

For the past decade or so, the Universal Verification Methodology (UVM) has been the de facto verification methodology supported by the entire EDA industry. But as chips become more heterogeneous, ...
EDN

Reuse existing verification assets with the Portable Test and Stimulus Standard

The productivity promise of portable stimulus has rapidly become well known in our industry. The high level of interest exhibited in the Accellera Portable Test and Stimulus Standard (PSS) makes sense ...
Semiconductor Engineering

The Lost Art Of Processor Verification

As we celebrate over 50 years of microprocessors, the industry has embraced every generation of silicon process technology with architectural innovation plus new design methods that have supported ...