Ars Technica

Open Source VHDL (or similar) CPU Simulation Software

Hey all, my last semester of college we had to develop the microarchitecture for a RISC processor. My group was ultimately unsuccessful (our L2 cache had some serious issues), but I wouldn't mind ...
EDN

Synopsys pulls VHDL and Verilog together and boosts speed

Synopsys has reworked a number of routines in its VCS hardware simulation tool in an attempt to improve performance at both the gate and RTL level to the point where the company reckons it now has the ...
Design-Reuse

Xilinx and EV Engineering deliver MHz co-simulation with Virtex-II technology

Based on the advanced Virtex-IITM FPGAs ZeBu accelerates co-simulation of designs driven by Verilog/VHDL/C/C++/SystemC testbenches PARIS, France, April 22, 2002 ...
Design-Reuse

Xilinx Slashes Simulation Time From Months To Minutes With Next Generation Software Platform For High-Speed DSP Design

v3.1 of industry leading System Generator for DSP tool adds new capabilities including hardware simulation supported by multiple DSP board suppliers SAN JOSE, Calif., March 17, 2003 - Xilinx, Inc., ...
New Electronics

Aldec fpga simulation technology added to Altium Designer

Altium and Aldec have signed an OEM agreement that adds Aldec's fpga simulation capabilities to Altium Designer. The agreement adds an extra dimension for electronics designers working with fpgas and ...
Business Wire

Altium Adds Aldec FPGA Simulation Technology to Altium Designer

SYDNEY--(BUSINESS WIRE)--Altium Limited (ASX:ALU) and Aldec, Inc. have signed an OEM agreement that adds Aldec's FPGA simulation capabilities to Altium Designer. This agreement adds an extra dimension ...