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Cadence Virtuoso Tutorial: CMOS XOR Gate Schematic Symbol and Layout
Basic Tutorial on creating a CMOS XOR Gate schematic symbol and layout using Cadence Virtuoso. Simulation not included as viewers are encouraged to implement and simulate their own designs. Technology: NCSU_CDK_TSMC02d 180nm XOR Picture Courtesy of Wikipedia: https://en.wikipedia.org/wiki/XOR_gate#/media/File:CMOS_XOR_Gate.svg
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